The invention relates generally to integrated circuits, and more particularly, to a magnetic random access memory for use in a semiconductor integrated circuit.
Conventional non-volatile random access memory ("RAM"), such as those used on a flat-shaped or spherical-shaped semiconductor integrated circuits, is a comparatively expensive circuit to produce. For one, it typically takes from 15 to 30 mask levels to implement the complicated memory cell structure. Also, many ion implantation processes and vacuum processes are necessary, thereby requiring a very long process time. Further, memory cells (especially dynamic memory cells) tend to leak and therefore require maintenance or refreshing circuitry. Further still, memory density (e.g., the number of memory cells per unit area) is always desired to be as large as possible to reduce the size requirements and/or increase the number of memory cells in the integrated circuit.
Some attempts have been made at alternate types of high density RAM. For example, in Tehrani, S., Chen, E., Durlam, M., Zhu, T., and Goronkin, H. (1996), "High Density Nonvolatile Magnetoresistive RAM," IEDM, IEDM 96-193 to 194, a non-volatile memory cell based on Ferro-magnetically coupled giant magneto-resistive material is disclosed. In Lyu, J S., Kim, B W., Kim, K H., Cha, J Y., Yoo, H J (1996), "Metal-Ferroelectric-Semiconductor Field-Effect Transistor (MFSFET) for Single Transistor Memory by Using Poly-Si Source/Drain and BaMgF.sub.4 Dielectric," IEDM, IEDM 96-503 to 506, a MFSFET with polysilicon islands as source/drain electrodes and BaMgF.sub.4 film as a gate dielectric is disclosed. However, both of these alternatives have not achieved an optimal solution for designing and manufacturing the MRAM with minimum impact to the design and manufacturing processes.